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EverBrain is a Strategy of Your Life

CONSULTANT
in charge

¹Ú»ó¹®

¹Ú»ó¹® ÄÁ¼³ÅÏÆ®

02-553-7973

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SOC ¼³°è

JOB INFORMATION

ȸ»ç¼Ò°³ Company
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Á÷±Þ/Á÷Ã¥ Position
 
´ã´ç¾÷¹« Work
°æ·Â (5~20³â)    

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* SOC ¼³°è

Áö¿øÀÚ°Ý          

* RTL (Verilog), C¾ð¾î Çʼö

* IP Verification & Design °æÇèÀÚ

* SOC(Application Processor) Full-chip Design À¯°æÇèÀÚ ¿ì´ë

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* SOC¸¦ À§ÇÑ Security À¯°æÇèÀÚ ¿ì´ë

* High Speed Serial Interface IP¿¡ ´ëÇÑ À¯°æÇèÀÚ ¿ì´ë

* Broadcasting System À¯°æÇèÀÚ ¿ì´ë

* ¹ÝµµÃ¼ ¼³°è ÇÁ·ÎÁ§Æ® ¸Å´ÏÁö¸ÕÆ® À¯°æÇèÀÚ ¿ì´ë (À̷¼­ Á¦Ãâ½Ã Ç¥½Ã ¿ä¸Á)

* ¿µ¾î °¡´ÉÀÚ ¿ì´ë

 

°æ·Â (3~12³â)    

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* SOC Front-End

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* Synthesis, Static Timing Analysis, Logic Equivalence Check °æÇèÀÚ

* DFT (Scan/BIST/JTAG) °æÇèÀÚ

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* CDC(Clock-Domain-Cross) Check À¯°æÇèÀÚ ¿ì´ë

* Full Chip/Layout Interface À¯°æÇèÀÚ, Tcl/Perl »ç¿ëÀÚ, ¿µ¾î °¡´ÉÀÚ ¿ì´ë

 

°æ·Â (5~12³â)    

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* SOC RTL Designer(DRAM°ü·Ã °æÇèÀÚ)

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* AP(Application Processor) °æÇèÀÚ

* DRAM(DDR3,4,LPDDR4 µî) À¯°æÇèÀÚ

  - PHY ¹× DRAM Interface °æÇèÀÌ ¸¹¾Æ¾ßÇÏ°í, ºü¸¥ µ¿ÀÛ¼Óµµ °æÇèÀÚ ¿ì´ë(1.6GHz)

* Verilog RTL,  Cadence & Synopsys Simulation ȯ°æ, Synthesis (DC), Timing Analysis (PrimeTime)

±Ù¹«Áö Location
¼­¿ï
ó¿ìÁ¶°Ç Condition
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Skills and Experience Required

Çз Education
´ëÁ¹ÀÌ»ó
°æ·Â Career
 
Ư±â»çÇ× Etc
 

JOB APPLY

Consultant
¹Ú»ó¹®
Inquire TEL.
02-553-7973
Submit via Email
sam@everbrain.com
Á¢¼ö¹æ¹ý Apply Method
Application On Line